A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

被引：2

作者：

Zhu, Jia-He ^{[1
]}

Wang, Da-Wei ^{[1
,2
]}

Zhao, Wen-Sheng ^{[1
]}

Dai, Jia-Yun ^{[3
]}

Wang, Gaofeng ^{[1
]}

机构：

[1] Hangzhou Dianzi Univ, MOE Engn Res Ctr Smart Microsensors & Microsyst, Sch Elect & Informat, Hangzhou 310018, Peoples R China

[2] State Key Lab Millimeter Waves, Nanjing 210096, Peoples R China

[3] Sci & Technol Monolith Integrated Circuits & Modu, Nanjing 210016, Peoples R China

来源：

ELECTRONICS | 2021年 / 10卷 / 18期

基金：

中国国家自然科学基金;

关键词：

vertical MOSFET; through-oxide-via; silicon-on-insulator; electrothermal simulation; self-heating effect; EVOLUTION; STACKING; MODEL; BODY;

D O I：

10.3390/electronics10182241

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, an innovative vertical MOSFET based on through-oxide via (TOV) technology is proposed for silicon-on-insulator (SOI)-based monolithic 3-D ICs. The proposed vertical MOSFET is investigated numerically. It was found that SOI can effectively reduce the parasitic capacitance, leakage current, power consumption, as well as suppress the pulse current interference of the substrate. The simulated results indicate that the proposed MOSFET possesses excellent characteristics in saturation current over 1500 mu A, sub-threshold swing of 69 mV/dec, and on/off current ratio of 1.28 x 10(11). Moreover, as temperature is a critical factor for the performance degradation of semiconductor devices, electrothermal simulations are conducted to predict the influence of the self-heating effect on device characteristics. The results show that device characteristics slightly deteriorate, but can still acceptable in their applications.

引用

页数：13

共 50 条

[31] An Effective Model for Evaluating Vertical Propagation Delay in TSV-based 3-D ICs
Watanabe, Masayuki
Niioka, Nanako
Kobayashi, Tetsuya
Karel, Rosely
Fukase, Masa-aki
Imai, Masashi
Kurokawa, Atsushi
PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015), 2015, : 514 - 518
[32] Monolithic 3-D silicon photonics
Koonath, P
Indukuri, T
Jalali, B
JOURNAL OF LIGHTWAVE TECHNOLOGY, 2006, 24 (04) : 1796 - 1804
[33] Thermal via planning for 3-D ICs
Cong, J
Zhang, Y
ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, : 745 - 752
[34] Power Distribution Paths in 3-D ICs
Pavlidis, Vasilis F.
De Micheli, Giovanni
GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, 2009, : 263 - 268
[35] Fast 3-D Electrothermal Device/Circuit Simulation of Power Superjunction MOSFET Based on SDevice and HSPICE Interaction
Chvala, Ales
Donoval, Daniel
Marek, Juraj
Pribytny, Patrik
Molnar, Marian
Mikolasek, Miroslav
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (04) : 1116 - 1122
[36] Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs
Hung, Shao-Chun
Lu, Yi-Chen
Lim, Sung Kyu
Chakrabarty, Krishnendu
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 29 (11) : 1875 - 1888
[37] A Scan-Chain-Based Built-in Self-Test for ILV in Monolithic 3-D ICs
Chen, Tian
Ding, Ruiyuan
Liu, Jun
Yuan, Xiaohui
Lu, Yingchun
Liang, Huaguo
Liu, Siyuan
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2024, 73
[38] Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs
Hung, Shao-Chun
Banerjee, Sanmitra
Chaudhuri, Arjun
Kim, Jinwoo
Lim, Sung Kyu
Chakrabarty, Krishnendu
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 42 (11) : 4296 - 4309
[39] Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines
Chaourani, Panagiotis
Rodriguez, Saul
Hellstrom, Per-Erik
Rusu, Ana
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 27 (02) : 468 - 480
[40] Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs
Song, Taigon
Liu, Chang
Peng, Yarui
Lim, Sung Kyu
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (05) : 1636 - 1648

← 1 2 3 4 5 →