Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs

被引：15

作者：

Song, Taigon ^{[1
]}

Liu, Chang ^{[2
]}

Peng, Yarui ^{[1
]}

Lim, Sung Kyu ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

[2] Broadcom Corp, Irvine, CA 92617 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2016年 / 24卷 / 05期

基金：

美国国家科学基金会;

关键词：

3-D IC; coupling; crosstalk; full chip; signal integrity (SI); through-silicon via (TSV); TSV; SILICON;

D O I：

10.1109/TVLSI.2015.2471098

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Through-silicon-via (TSV)-to-TSV coupling is a new phenomenon in 3-D ICs, and it becomes a significant source of signal integrity problems. The existing studies on its extraction and analysis, however, become inaccurate when handling more than two TSVs on full-chip scale. In this paper, we investigate the multiple TSV-to-TSV coupling issue and propose a model that can be efficiently used for full-chip extraction. Then, we perform an analysis on the impact of TSV parasitics on coupling and delay. Unlike the common belief that only the closest neighboring TSVs affect the victim, this paper shows that nonneighboring aggressors also cause nonnegligible coupling noise. Based on these observations, we propose an effective method of reducing the overall coupling level.

引用

页码：1636 / 1648

页数：13

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