Partial TMR in FPGAs using Approximate Logic Circuits

被引：0

作者：

Sanchez-Clemente, A. ^{[1
]}

Entrena, L. ^{[1
]}

Garcia-Valderas, M. ^{[1
]}

机构：

[1] Univ Carlos III Madrid, Dept Elect Technol, Avda Univ 30, Leganes, Madrid, Spain

来源：

2015 15TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS (RADECS) | 2015年

关键词：

Single Event Upset; Triple Modular Redundancy; FPGA; Approximate circuit; selective mitigation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

TMR is a very effective technique to mitigate SEU effects in FPGAs, but it is often expensive in terms of FPGA resource utilization and power consumption. For certain applications, Partial TMR can be used to trade off the reliability with the cost of mitigation. In this work we propose a new approach to build Partial TMR circuits for FPGAs using approximate logic circuits. This approach is scalable, with a low granularity, and can provide an optimal balance between reliability and overheads. The proposed approach has been validated using fault injection.

引用

页数：4

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