On customized decimation filter implementation

被引：0

作者：

Naviner, LAD ^{[1
]}

Naviner, JF ^{[1
]}

机构：

[1] GET Telecom Paris, CNRS, LTCI, F-75013 Paris, France

来源：

2004 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT), VOLS. 1- 3 | 2004年

关键词：

decimation alter; dedicated processors; hardware implementation; digital alterarchitecture;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper deals with customized implementation of decimation processors. Important aspects of design low decisions are considered under hardware impact point of view. Several implementation approaches and respective evaluations in terms of time and basic operators requirements are given as well as a summary of the steps involved in an ad hoc implementation.

引用

页码：304 / 309

页数：6

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