A 1 GHz decimation filter for σ-δ ADC

被引：0

作者：

Lian, Yong ^{[1
]}

Wei, Ying ^{[1
]}

Chandrasekaran, Rajasekaran ^{[1
]}

机构：

[1] Natl Univ Singapore, Dept ECE, Singapore 117548, Singapore

来源：

2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3 | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the implementation of a high-speed decimation filter operating at Giga Hertz that is suitable for high-speed Delta-Sigma analog-to-digital converters. The filter is realized in a non-recursive architecture using a novel full adder and D flip-Sop. The filter has been implemented in a 0.18 mu m/1.8 V CMOS technology for a decimation factor of 4. The operation frequency is 1 GHz and the power consumption of I and Q filters are 6 mW and 4 mW, respectively.

引用

页码：342 / 345

页数：4

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