Soft error hardened latch scheme for enhanced scan based delay fault testing

被引：2

作者：

Ikedai, Takashi ^{[1
]}

Namba, Kazuteru ^{[1
]}

Ito, Hideo ^{[1
]}

机构：

[1] Chiba Univ, Grad Sch Sci & Technol, Inage Ku, Chiba 2638522, Japan

来源：

DFT 2007: 22ND IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2007年

关键词：

D O I：

10.1109/DFT.2007.44

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In recent high-density, high-speed and low-power VLSIs, soft errors (M) and delay faults (DFs) frequently occur. Therefore, SE hardened design and DF testing are essential. This paper proposes three types of scan flip-flops (FFs) which have SE tolerant capability and allow enhanced scan shifting for DF testing, i.e. arbitraty two-pattern testing. The slave latches used in these FFs are constructed by adding some extra transistors which make enhanced scan shifting possible fir DF testing on an existing SE hardened latch. The areas and time overheads of the proposed latches are tip to 33.3% and 31.4% larger than those of the existing SE hardened latch respectively. However, the areas of the proposed FFs are about 30% smaller than existing FFs which have SE tolerant capability and allow enhanced scan shifting for DF testing.

引用

页码：282 / 290

页数：9

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