HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

被引：1

作者：

Wei, Zhenqi ^{[1
]}

Liu, Peilin ^{[1
]}

Sun, Rongdi ^{[1
]}

Zhou, Zunquan ^{[1
]}

Jin, Ke ^{[1
]}

Zhou, Dajiang ^{[2
]}

机构：

[1] Shanghai Jiao Tong Univ, Dept Elect Engn, 800 Dongchuan Rd, Shanghai 200240, Peoples R China

[2] Waseda Univ, Grad Sch Informat Prod & Syst, 2-7 Hibikino, Kitakyushu, Fukuoka 8080135, Japan

来源：

IEICE ELECTRONICS EXPRESS | 2016年 / 13卷 / 14期

关键词：

NoC; DMA; packet-circuit switching; circuit setup; bidirectional link;

D O I：

10.1587/elex.13.20160529

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With a growing number of cores integrated in a single chip, the efficiency of inter-core direct memory access (DMA) transfers has an increasingly significant impact on the overall performance of parallel applications running on network-on-chip (NoC) processors. In this paper we propose HyDMA, a low-latency inter-core DMA approach based on a hybrid packet-circuit switching NoC. With dynamic setup and lengthening of circuit channels composing of bidirectional links, HyDMA can achieve both high flexibility of packet switching and low communication latency of circuit switching for concurrent DMA transfers. Experimental results prove HyDMA exhibits high efficiency with marginal hardware overhead.

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页数：12

共 37 条

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