共 50 条
- [42] self-aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement Impact DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION VII, 2013, 8684
- [45] Practical application of full-feature alternating phase-shifting technology for a phase-aware standard-cell design flow 38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 93 - 96
- [46] Process results using automatic pitch decomposition and double patterning technology (DPT) at k1eff <0.20 PHOTOMASK TECHNOLOGY 2006, PTS 1 AND 2, 2006, 6349
- [47] Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library 2016 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2016, : 673 - 678
- [48] Design Technology Co-optimization for 14/10nm Metal1 Double Patterning Layer DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY X, 2016, 9781
- [49] Configurable Redundant Via-Aware Standard Cell Design Considering Multi-Via Mechanism PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013), 2013, : 322 - 326
- [50] Architectural strategies in standard-cell design for the 7 nm and beyond technology node JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2016, 15 (01):