A 10-bit 40MS/s low power SHA-less pipelined ADC for System-On-Chip Digital TV Application

A pipelined analog to digital converter which is suitable for low power applications incorporating merged capacitor sharing (MCS) technique is presented. The resolution of the pipelined ADC is improved by sharing an op-amp between two pipelined stages and removing the front end Sample-and-Hold amplifier (SHA). The proposed technique reduces the aperture error due to the absence of SHA and op-amp sharing. The proposed ADC is implemented in 0.18 mu m CMOS technology which occupies a die area of 1.3 mm(2). The differential and integral non-linearity of the pipelined ADC is +0.32/-0.32LSB and +0.67/-0.67LSB respectively. The ADC achieves an SNDR of 55.67dB and exhibits an FOM of 0.49 pJ/conversion-step while drawing 9.77mW from a 1.8V power supply.