Floating Point STAP Implementation on FPGAs

被引：0
|
作者：
Mauer, Volker [1 ]
Parker, Michael [2 ]
机构：
[1] Altera Corp, European Technol Ctr, High Wycombe, Bucks, England
[2] Altera Corp, San Jose, CA USA
来源：
2011 IEEE RADAR CONFERENCE (RADAR) | 2011年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
STAP has increased the processing requirements for radar to a point where implementation on CPUs is no longer an option. At the same time, the highly iterative algorithm poses precision requirements that are difficult and inefficient to address using conventional fixed point implementations on FPGAs. This paper focuses on the most computationally intensive parts of the algorithm, QR decomposition, and demonstrates how it can be mapped efficiently in floating point onto FPGAs. For QRD, a variation of the modified Gram-Schmidt algorithm is developed that increases precision and minimizes latency when implemented on FPGAs.
引用
收藏
页码：901 / 904
页数：4
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