Floating Point STAP Implementation on FPGAs

STAP has increased the processing requirements for radar to a point where implementation on CPUs is no longer an option. At the same time, the highly iterative algorithm poses precision requirements that are difficult and inefficient to address using conventional fixed point implementations on FPGAs. This paper focuses on the most computationally intensive parts of the algorithm, QR decomposition, and demonstrates how it can be mapped efficiently in floating point onto FPGAs. For QRD, a variation of the modified Gram-Schmidt algorithm is developed that increases precision and minimizes latency when implemented on FPGAs.