A 400-MS/s 8-b 2-b/cycle SAR ADC with Shared Interpolator and Alternative Comparators

A 400-MS/s 8-b SAR ADC with 2-b/cycle conversion is presented in this paper. Compared with conventional SAR structure, an AUX-DAC is proposed to achieve high switch energy efficiency and low power. The proposed structure of ADC uses a shared interpolator, which not only reduces one DAC, but also separates the input signal from the comparator to reduce the kickback noise. To further increase the speed, the logic delay is reduced by the comparators working alternatively and the results directly sent to the M-DAC. Foreground calibration is used to calibrate the offset of the comparators. The post simulation results show that the ADC achieves a SNDR of 48dB, power consumption of 5.6mW and FoM of 67fF/conversion-step at 400MS/s rate with 1.2 V supply voltage.