共 50 条
- [1] High Robustness Energy- and Area-Efficient Dynamic-Voltage-Scaling 4-phase 4-rail Asynchronous-Logic Network-on-Chip (ANoC) [J]. 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 1913 - 1916
- [3] An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic [J]. Circuits, Systems, and Signal Processing, 2018, 37 : 1863 - 1883
- [5] Energy- and area-efficient deinterleaving architecture for high-throughput wireless applications [J]. INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2004, 3254 : 218 - 227
- [7] Area-Efficient Partial-Clique-Energy MRF Pair Design with Ultra-Low Supply Voltage [J]. 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 261 - 264
- [8] An energy- and area-efficient limiting amplifier with interleaving feedback for 25 Gb/s optical receiver [J]. IEICE ELECTRONICS EXPRESS, 2021, 18 (08):
- [9] Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application [J]. PROCEEDINGS OF 2016 IEEE INTERNATIONAL SYMPOSIUM ON NANOELECTRONIC AND INFORMATION SYSTEMS (INIS), 2016, : 244 - 249
- [10] Energy-/Area-Efficient Spintronic ANN-based Digit Recognition via Progressive Modular Redundancy [J]. 2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS, 2023,