Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application

Error detectors/predictors are inevitable for any power and performance constrained designs. Dynamic voltage and frequency scaling can be efficiently implemented using these error detectors/predictors. In this work, we propose a new area and power efficient error predictor for dynamic voltage and frequency scaling application. In the proposed error predictor, the edge of delayed data of master latch is observed in the high phase of the clock to flag a warning signal. The warning signal determines the point of reduction in the supply voltage without any system failure. Compared to pulse-based error predictor, our timing error predictor consumes 17% less power under 100% switching activity and requires 27% less additional area overhead. The functionality of the proposed FF is tested by implementing ISCAS89 benchmark circuits, 16-bit adder, and 16-bit multiplier. A fully automated insertion flow is adopted to implement the block level designs. Using the proposed FF in a block level implementation shows that it can save power up to 33% in the typical corner compared to conventional worst case design.