Parametric Timing Analysis and Its Application to Dynamic Voltage Scaling

被引：10

作者：

Mohan, Sibin ^{[1
]}

Mueller, Frank ^{[1
]}

Root, Michael ^{[2
]}

Hawkins, William ^{[2
]}

Healy, Christopher ^{[2
]}

Whalley, David ^{[3
]}

Vivancos, Emilio ^{[4
]}

机构：

[1] N Carolina State Univ, Dept Comp Sci, Ctr Embedded Syst Res, Raleigh, NC 27695 USA

[2] Furman Univ, Dept Comp Sci, Greenville, SC 29613 USA

[3] Florida State Univ, Dept Comp Sci, Tallahassee, FL 32306 USA

[4] Univ Politecn Valencia, Dept Sistemas Informat & Computac, Valencia 46022, Spain

来源：

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | 2010年 / 10卷 / 02期

关键词：

Algorithms; Experimentation; Real-time systems; worst-case execution time; timing analysis; dynamic voltage scaling; CACHE; PIPELINE;

D O I：

10.1145/1880050.1880061

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Embedded systems with real-time constraints depend on a priori knowledge of worst-case execution times (WCETs) to determine if tasks meet deadlines. Static timing analysis derives bounds on WCETs but requires statically known loop bounds. This work removes the constraint on known loop bounds through parametric analysis expressing WCETs as functions. Tighter WCETs are dynamically discovered to exploit slack by dynamic voltage scaling (DVS) saving 60% to 82% energy over DVS-oblivious techniques and showing savings close to more costly dynamic-priority DVS algorithms. Overall, parametric analysis expands the class of real-time applications to programs with loop-invariant dynamic loop bounds while retaining tight WCET bounds.

引用

页数：34

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