A High Speed Low Power Capacitorless SOI-DRAM Cell Using Impact Ionization and GIDL Effect

A high speed low power capacitorless SOI-DRAM cell using impact ionization and GIDL effect for write "1" operation was proposed. The conventional capacitorless DRAM cell with single mechanism is either high speed or low power, while the proposed DG-FinFET cell employs the efficient integration of impact ionization and GIDL effects by adopting negative bias on back gate to couple the front and back gates, yielding high speed low power performance. The simulation results demonstrate ideal characteristics in both cell operations and power consumption. The write operation of the cell is within ins attributed to the impact ionization effect. Low power consumption is achieved by using GIDL because the coupling between the front and back gates restrains the impact ionization current. The ratio of read "1" and read "0" current is more than 9.38E5. Moreover, the cell is non-destructive in read operation and has large sense margin and great retention characteristics.