Study of chip strength due to backside grinding on wafer

被引:0
|
作者
Chen, SL [1 ]
Tsai, CZ
Hung, KC
Wu, EB
机构
[1] Natl Taiwan Univ, Inst Appl Mech, Taipei 106, Taiwan
[2] Macronix Int Co Ltd, Hsinchu 300, Taiwan
关键词
chip strength; weak region on wafer; backside grinding; grinding mark;
D O I
10.1080/02533839.2005.9671056
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The strength distribution of semiconductor chips on a wafer was studied for this paper using the three-point bending test method that complies with ASTM standard E855. It was found from thousands of testing results that a weak region in a wafer always exists when the wafer has been thinned by mechanical backside grinding method. This weak region was distributed in two sectorial regions 45 degrees wide and symmetric to the wafer center. The averaged chip strength in the weak region was found to be at least 30% lower than the averaged chip strength of the whole wafer, and was independent of chip aspect ratio, metallization, diameter of the wafer, and the equipment that the backside grinding process used. The existence of the weak region was due to the grinding mark produced by the equipment, and was physically explained by the experimental results in this study. This weak region was able to be eliminated by using either plasma etching or polishing after the mechanical backside grinding,
引用
收藏
页码:859 / 866
页数:8
相关论文
共 50 条
  • [1] SILICON-WAFER DEFORMATION AFTER BACKSIDE GRINDING
    BLECH, I
    DANG, D
    SOLID STATE TECHNOLOGY, 1994, 37 (08) : 74 - 76
  • [2] Modeling and simulation of silicon wafer backside grinding process
    Li, Zhaoqiang
    Jing, Xiangmeng
    Jiang, Feng
    Zhang, Wenqi
    2014 15TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2014, : 874 - 877
  • [3] Study on the effects of wafer thinning and dicing on chip strength
    Chen, SL
    Tsai, CZ
    Wu, EB
    Shih, IG
    Chen, YN
    IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2006, 29 (01): : 149 - 157
  • [4] Dynamic Finite Element Modeling of Backside Grinding Process for TSV Wafer
    Sun Bo
    Qin Fei
    Sun Jinglong
    Chen Pei
    An Tong
    2017 18TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2017, : 894 - 897
  • [5] An Investigation on the Total Thickness Variation Control and Optimization in the Wafer Backside Grinding Process
    Liu, Yuanhang
    Tao, Hongfei
    Zhao, Dewen
    Lu, Xinchun
    MATERIALS, 2022, 15 (12)
  • [6] A Comparison Study of Different Wafer Backside Coating Technologies
    Hwa, Loh Kian
    Erfe, Eric
    2014 IEEE 36TH INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY CONFERENCE (IEMT), 2015,
  • [7] Influence of grinding process on semiconductor chip strength
    Wu, EB
    Shih, IG
    Chen, YN
    Chen, SC
    Tsai, CZ
    Shao, CA
    52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, : 1617 - 1621
  • [8] Study on grinding processing of sapphire wafer
    Ebina, Yutaro
    Hang, Wei
    Zhou, Libo
    Shimizu, Jun
    Teppei, Onuki
    Ojima, Hirotaka
    Tashiro, Yoshiaki
    ADVANCES IN ABRASIVE TECHNOLOGY XV, 2012, 565 : 22 - +
  • [9] Study into grinding force in back grinding of wafer with outer rim
    Xiang-Long Zhu
    Yu Li
    Zhi-Gang Dong
    Ren-Ke Kang
    Shang Gao
    Advances in Manufacturing, 2020, 8 : 361 - 368
  • [10] Study into grinding force in back grinding of wafer with outer rim
    Zhu, Xiang-Long
    Li, Yu
    Dong, Zhi-Gang
    Kang, Ren-Ke
    Gao, Shang
    ADVANCES IN MANUFACTURING, 2020, 8 (03) : 361 - 368