共 50 条
- [31] Sub-quarter micron SRAM cells stability in low-voltage operation: A comparative analysis [J]. 2002 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP - FINAL REPORT, 2002, : 168 - 171
- [32] A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM [J]. 2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, : 129 - 132
- [34] Merits of CMOS SIMOX technology for low-voltage SRAM macros [J]. NEC RESEARCH & DEVELOPMENT, 1999, 40 (03): : 287 - 291
- [36] MOS charge pumps for low-voltage operation [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (04) : 592 - 597
- [37] Comparative Evaluation of Tunnel-FET Ultra-Low Voltage SRAM Bitcell and Impact of Variations [J]. 2014 5TH EUROPEAN WORKSHOP ON CMOS VARIABILITY (VARI), 2014,
- [38] Design of a 3T Current Reference for Low-Voltage, Low-Power Operation [J]. 2018 INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2018), 2018, : 13 - 16
- [39] An Area Efficient Low-Voltage 6-T SRAM Cell Using Stacked Silicon Nanowires [J]. 2018 INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2018), 2018, : 117 - 120
- [40] Proposal of a New Ultra Low Leakage 10T Sub threshold SRAM Bitcell [J]. 2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2012, : 470 - 474