Subthreshold leakage modeling and estimation of general CMOS complex gates

被引：0

作者：

Butzen, Paulo F. ^{[1
]}

Reis, Andre I. ^{[2
]}

Kim, Chris H. ^{[3
]}

Ribas, Renato P. ^{[1
]}

机构：

[1] Univ Fed Rio Grande do Sul, Inst Informat, Porto Alegre, RS, Brazil

[2] Nangate Inc, Menlo Pk, CA USA

[3] Univ Minnesota, EECS, Minneapolis, MN 55455 USA

来源：

INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2007年 / 4644卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new subthreshold leakage model is proposed in order to improve the static power estimation in general CMOS complex gates. Series-parallel transistor arrangements with more than two logic depth, as well as non-series-parallel off-switch networks are covered by such analytical modeling. The occurrence of on-switches in off-networks, also ignored by previous works, is considered in the proposed analysis. The model has been validated through electrical simulations, taking into account transistor sizing, operating temperature, supply voltage and threshold voltage variations.

引用

页码：474 / +

页数：3

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