共 50 条
- [1] Test time reduction reusing multiple processors in a network-on-chip based architecture [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 62 - 63
- [2] RISO: Relaxed Network-on-Chip Isolation for Cloud Processors [J]. 2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2013,
- [3] Bandwidth Bottleneck in Network-on-Chip for High-Throughput Processors [J]. PACT '20: PROCEEDINGS OF THE ACM INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, 2020, : 157 - 158
- [5] Evaluation of Buffer Organizations for Network-on-Chip [J]. 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 1403 - 1405
- [7] High-Performance Adaption of ARM Processors into Network-on-Chip Architectures [J]. 2013 IEEE 26TH INTERNATIONAL SOC CONFERENCE (SOCC), 2013, : 222 - 227
- [8] Latency Analysis of Network-On-Chip based Many-Core Processors [J]. 2014 22ND EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP 2014), 2014, : 432 - 439
- [9] Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture [J]. ISMVL 2006: 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, 2006, : 38 - 43
- [10] Performance and Energy Evaluation of Network-On-Chip Infrastructure [J]. 2016 INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTATION TECHNOLOGIES (ICICT), VOL 3, 2015, : 848 - 852