On the reconfiguration algorithm for fault-tolerant VLSI arrays

In this paper, an improved algorithm is presented for the NP-complete problem of reconfiguring a two-dimensional degradable VLSI array under the row and column routing constraints. The proposed algorithm adopts the partial computing for the logical row exclusion so that the most efficient algorithm, cited in literature, is speeded up without loss of performance. In addition, a flaw in the earlier approach is also addressed. Experimental results show that our algorithm is approximately 50% faster than the above stated algorithm.