622-Mbit/s burst-mode clock and data recovery circuit with duty control in a jitter reduction circuit

被引：0
|
作者：
Park, CS
Lee, CG
Park, CS
机构：
[1] GIST, Dept Informat & Commun, Kwangju 500712, South Korea
[2] KOPTI, Photon Syst Lab, Kwangju 500210, South Korea
来源：
OPTICAL ENGINEERING | 2005年 / 44卷 / 08期
关键词：
burst-mode clock and data recovery; jitter reduction technique; gated oscillator; optical communications; passive optical network;
D O I：
10.1117/1.2012328
中图分类号：
O43 [光学];
学科分类号：
070207 ; 0803 ;
摘要：
A clock and data recovery circuit using the clock jitter reduction technique is proposed for a 622-Mbit/s burst-mode data stream. The clock jitter reduction is achieved by controlling the clock duty cycle with the phase information of the recovered clock. The proposed clock recovery circuit, based on the gated oscillator, recovers a low-jitter output clock with up to 4090 consecutive zeros. (c) 2005 Society of Photo-Optical Instrumentation Engineers.
引用
收藏
页数：4
相关论文
共 50 条
  • [41] Burst-mode clock and data recovery with FEC and fast phase acquisition for burst-error correction in GPONs
    Shastri, Bhavin J.
    Zeng, Julien Faucher Ming
    Plant, David V.
    [J]. 2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 2007, : 93 - 96
  • [42] Probabilistic Theory for Semi-Blind Oversampling Burst-Mode Clock and Data Recovery Circuits
    Shastri, Bhavin J.
    Plant, David V.
    [J]. 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 161 - 164
  • [43] A monolithic 10 Gb/s clock and data recovery circuit
    School of Physics Science and Technology, Nanjing Normal University, Nanjing, 210046, China
    不详
    [J]. Proc. China-Japan Jt. Microw. Conf., CJMW, 1600, (481-484):
  • [44] A Monolithic 10 Gb/s Clock and Data Recovery Circuit
    Hou Fenfei
    Cao Xiaowei
    [J]. 2008 CHINA-JAPAN JOINT MICROWAVE CONFERENCE (CJMW 2008), VOLS 1 AND 2, 2008, : 436 - +
  • [45] Digital Clock Data Recovery Circuit fot S/PDIF
    Kang, Jonghoon
    Lee, Chanho
    [J]. 2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2016, : 325 - 326
  • [46] AN ANALOG PLL-BASED CLOCK AND DATA RECOVERY CIRCUIT WITH HIGH INPUT JITTER TOLERANCE
    SUN, SYS
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (02) : 325 - 330
  • [47] Burst-mode clock and data recovery in optical multiaccess networks using broad-band PLLs
    Li, A
    Faucher, J
    Plant, DV
    [J]. IEEE PHOTONICS TECHNOLOGY LETTERS, 2006, 18 (1-4) : 73 - 75
  • [48] A new 1.25-Gb/s burst mode Clock and Data Recovery circuit using two Digital Phase Aligners and a Phase Interpolator
    Seong, Chang-Kyung
    Lee, Seung-Woo
    Choi, Woo-Young
    [J]. IEICE TRANSACTIONS ON COMMUNICATIONS, 2008, E91B (05) : 1397 - 1402
  • [49] A monolithic 622Mb/s half rate clock and data recovery circuit utilizing a novel linear phase detector
    Jiun, CH
    Zulkifli, TZA
    Aziz, ZAA
    Noh, NM
    [J]. TENCON 2004 - 2004 IEEE REGION 10 CONFERENCE, VOLS A-D, PROCEEDINGS: ANALOG AND DIGITAL TECHNIQUES IN ELECTRICAL ENGINEERING, 2004, : D348 - D351
  • [50] A novel digital phase interpolation control for clock and data recovery circuit
    Liu, Huihua
    Li, Lei
    Li, Ping
    Zhang, Jun
    [J]. IEICE ELECTRONICS EXPRESS, 2015, 12 (21):
12345