High-Speed Communication System Development using FPGA based CAM Implementation

被引:0
|
作者
Banerjee, Tribeni Prasad [1 ]
Konar, Amit [2 ]
Chowdhury, Joydeb Roy [1 ]
机构
[1] Cent Mech Engn Res Inst, Durgapur 713209, W Bengal, India
[2] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata, India
关键词
Signal Processing; DSP; FPGA; ASIC; SoC; Data-Compression; CAM; Image and Video compression;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper we propose a Lossless data compressor in high level throughput using re programable FPGA technology.Real time data compression is expected to play a crucial role in high rate data communication applications. Most available approaches have largely overlooked the impact of mixed pixels and subpixel targets, which can be accurately modeled and uncovered by resorting to the wealth of spectral information provided by hyperspectral image data. In this paper, we proposed an FPGA -based data compressor on the concept of CAM and Dictionary based compression technique has been proposed in this paper. It has been implemented on a Xilinx Spartan3 -II FPGA formed by several millions of gates, and with high computational power and compact size, which make this reconfigurable device very appealing for onboard, real-time data processing.
引用
收藏
页码:252 / +
页数:3
相关论文
共 50 条
  • [31] High-speed FPGA Implementation of an Improved LMS Algorithm
    Dong, Xianglei
    Li, Huiyong
    Wang, Yu
    2013 INTERNATIONAL CONFERENCE ON COMPUTATIONAL PROBLEM-SOLVING (ICCP), 2013, : 342 - 345
  • [32] High-Speed Power Allocation in NOMA System Using FPGA-Based DNN
    Yanamala, Rama Muni Reddy
    Pullakandam, Muralidhar
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2024, 33 (14)
  • [33] Design and Development of High-speed Data Acquisition System with Cyclone FPGA
    Kumar, Arvinda C. S.
    Premananda, B. S.
    Kumar, K. J.
    7TH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT 2016), 2016,
  • [34] Design and Implementation of High-Speed Real-Time Data Acquisition and Processing System based on FPGA
    Zhou, Guojuan
    Xiong, Guocan
    Yu, Fuhua
    Sun, Wen'E
    PROCEEDINGS OF THE 2016 2ND INTERNATIONAL CONFERENCE ON SOCIAL SCIENCE AND TECHNOLOGY EDUCATION (ICSSTE 2016), 2016, 55 : 514 - 519
  • [35] High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation
    Thamizharasan, V.
    Kasthuri, N.
    IETE JOURNAL OF RESEARCH, 2023, 69 (05) : 2301 - 2309
  • [36] FPGA Implementation and Examination of Efficiency in a High-Speed PMSM Drive System Based on Direct Torque Control
    Yasumura, Kohei
    Inoue, Yukinori
    Morimoto, Shigeo
    Sanada, Masayuki
    2017 IEEE 12TH INTERNATIONAL CONFERENCE ON POWER ELECTRONICS AND DRIVE SYSTEMS (PEDS), 2017, : 343 - 348
  • [37] FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code
    Mandal, Swagata
    Sau, Suman
    Chakrabarti, Amlan
    Pal, Susanta Kumar
    Chattopadhyay, Subhasish
    2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS), 2015, : 169 - 174
  • [38] Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA
    Jin, Seunghun
    Kim, Dongkyun
    Thuy Tuong Nguyen
    Kim, Daijin
    Kim, Munsang
    Jeon, Jae Wook
    IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, 2012, 8 (01) : 158 - 167
  • [39] High-speed image feature detection using FPGA implementation of fast algorithm
    Kraft, Marek
    Schmidt, Adam
    Kasinski, Andrzej
    VISAPP 2008: PROCEEDINGS OF THE THIRD INTERNATIONAL CONFERENCE ON COMPUTER VISION THEORY AND APPLICATIONS, VOL 1, 2008, : 174 - 179
  • [40] FPGA-based Current Controller for High-speed Communication and Real-time Control System
    Li, Tianjian
    Fujimoto, Yasutaka
    IECON 2008: 34TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, VOLS 1-5, PROCEEDINGS, 2008, : 161 - 166