SEU Tolerant Latch Based on Error Detection

被引：29

作者：

She, Xiaoxuan ^{[1
]}

Li, N. ^{[2
]}

Tong, J. ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China

[2] Gpix Inc, Orlando, FL 33816 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2012年 / 59卷 / 01期

关键词：

Hardened by design; latch; radiation effects; single event upset (SEU); SOFT ERRORS; RELIABILITY; DELAY;

D O I：

10.1109/TNS.2011.2178265

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an SEU hardened latch that can mitigate SEU based on an error detection circuit and a multiplexer. During the hold phase, an SEU on an internal node may upset the logic state of the latch. But the error detection circuit can detect this fault and generate fault indication signals via precharge and discharge operations. The fault indication signals control a multiplexer to select a correct output. Therefore, each latch has some error detection and correction capability.

引用

页码：211 / 214

页数：4

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