JFETIDG: A Compact Model for Independent Dual-Gate JFETs

被引：0
|
作者：
Xia, Kejun [1 ]
McAndrew, Colin C. [1 ]
Sheng, Hanyu [1 ]
机构：
[1] NXP Semicond, Tempe, AZ USA
来源：
2017 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM) | 2017年
关键词：
JFET; device modeling; SPICE; VOLTAGE;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a new compact model, JFETIDG, for independent dual-gate JFETs. The model is applicable to JFETs with any combination of p-n junction or MOS gates, captures geometry and temperature dependencies. As a special case, it can model junctionless MOSFETs. The model is verified by comparison to experimental and TCAD data. Verilog-A code for the model is available in the public domain.
引用
收藏
页码：124 / 125
页数：2
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