Reliability study of high-pin-count flip-chip BGA

被引:0
|
作者
Li, Y [1 ]
Xie, J [1 ]
Verma, T [1 ]
Wang, V [1 ]
机构
[1] Altera Corp, San Jose, CA 95134 USA
关键词
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
A family of 1.0-mm pitch full-array flip-chip BGAs were developed. These packages vary from 27 to 45 mm in package size, 15 to 25 mm in die size, and 672 to 1020 in ball count. With dies and packages so large, solder joint fatigue failure and underfill delamination, induced by thermal expansion mismatch, are a major concern. Finite element analysis was set up for efficient reliability analysis. Two substrates, hi-CTE ceramic (12x10(-6) /degreesC) and BT (17x10(-6 /degrees)C), are compared. Hi-CTE ceramic substrate has a better CTE match with die (2.6x10(-6) /degreesC), therefore, it was surmised that hi-CTE ceramic would improve component-level reliability yet with satisfactory board-level reliability. To validate it, several die and package combinations were modeled using both substrates. Both component-level stresses and board-level solder joint fatigue Life were compared. In addition, design of experiment (DOE) was used to study the effect of properties and dimensions of underfill and heat spreader on solder joint fatigue life. The effect of pad opening size was also quantified. Finally, the effect of underfill on interface stress between underfill and die was investigated.
引用
收藏
页码:276 / 280
页数:5
相关论文
共 50 条
  • [21] Electrical Design and Demonstration of an Embedded High-pin-count LSI Chip Package
    Ohshima, Daisuke
    Sasaki, Hideki
    Mori, Kentaro
    Fujimura, Yuki
    Kikuchi, Katsumi
    Nakashima, Yoshiki
    Funaya, Takuo
    Nishiyama, Tomohiro
    Murakami, Tomoo
    Yamamichi, Shintaro
    2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 482 - +
  • [22] Reliability studies of two flip-chip BGA packages using power cycling test
    Qi, Q
    MICROELECTRONICS RELIABILITY, 2001, 41 (04) : 553 - 562
  • [23] Development of thin flip-chip BGA for package on package
    Suzuki, Yasuhiro
    Kayashima, Yuuji
    Maeda, Takehik
    Matsuura, Yoshihiro
    Sekiguchi, Tomobisa
    Watanabe, Akio
    57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS, 2007, : 8 - +
  • [24] Flip-chip BGA design to avert die cracking
    Han, JB
    JOURNAL OF ELECTRONIC PACKAGING, 2001, 123 (01) : 58 - 63
  • [25] Flip-chip BGA meets gigahertz packaging needs
    Hamano, T
    Ueno, S
    ELECTRONIC PRODUCTS MAGAZINE, 1999, : 30 - 31
  • [26] Thermally enhanced flip-chip BGA with organic substrate
    Matsushima, H
    Baba, S
    Tomita, Y
    Watanabe, M
    Hayashi, E
    Takemoto, Y
    48TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1998 PROCEEDINGS, 1998, : 685 - 691
  • [27] High-speed differential interconnection design for flip-chip BGA packages
    Yuan, W. L.
    Kuah, H. P.
    Wang, C. K.
    Sun, Anthony Y. S.
    Zhu, W. H.
    Tan, H. B.
    Muhamad, A. D.
    EPTC 2006: 8TH ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2006, : 76 - 81
  • [28] Flip chip and BGA solder joint reliability
    Ye, Hua
    Basaran, Cemal
    Hopkins, Doug
    Liu, Heng
    Cartwright, Alexander
    Advanced Packaging, 2003, 12 (05): : 17 - 19
  • [29] Pin Assignment Optimization for Large-Scale High-Pin-Count BGA Packages Using Particle Swarm Optimization Algorithm
    Jian, Qian-Hua
    Zhang, Mu-Shui
    Li, Zhuo-Yue
    Tan, Hong-Zhou
    2016 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC), 2016, : 250 - 252
  • [30] Flip-chip packaging reliability advances
    Alcoe, David
    Blackwell, Kim
    Laine, Eric
    Advanced Packaging, 2000, 9 (06):