Modeling of gate capacitance for deep sub-micron MOSFETs

被引:0
|
作者
Dai Yuehua [1 ]
Chen Junning
Ke Daoming
Zhu Dezhi
Xu Chao
机构
[1] Anhui Univ, Inst Elect Sci & Technol, Hefei 230039, Peoples R China
[2] Res Inst China Elect Technol Grp Corp, Hefei 230031, Peoples R China
来源
CHINESE JOURNAL OF ELECTRONICS | 2007年 / 16卷 / 03期
关键词
quantum mechanical effects; gate capacitance; inversion layer; polysilicon gate; POLYSILICON QUANTIZATION; MOS; VOLTAGE;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
With the scaling of MOSFET dimensions, the gate oxides become thinner. Due to the Quantum mechanical effects (QME's), the carrier distributions in the silicon substrate and polysilicon electrodes play more important role for the gate capacitance. Based on improved triangular potential well approximation and least-squares curve fit, a simplified analytical model combined the impact of quantum effects in inversion and polysilicon gate regions is proposed. The results of the model are compared and verified with the numerical simulation.
引用
收藏
页码:435 / 438
页数:4
相关论文
共 50 条
  • [41] MEASUREMENT OF THRESHOLD VOLTAGE AND CHANNEL LENGTH OF SUB-MICRON MOSFETS
    JAIN, S
    IEE PROCEEDINGS-I COMMUNICATIONS SPEECH AND VISION, 1988, 135 (06): : 162 - 164
  • [42] THE SERIES RESISTANCE OF SUB-MICRON MOSFETS AND ITS EFFECT ON THEIR CHARACTERISTICS
    KLAASSEN, FM
    BIERMANS, PTJ
    VELGHE, RMD
    JOURNAL DE PHYSIQUE, 1988, 49 (C-4): : 257 - 260
  • [43] Measuring and characterizing sub-micron short channel LDD MOSFETs
    Liu, PC
    Lin, H
    1999 INTERNATIONAL CONFERENCE ON MODELING AND SIMULATION OF MICROSYSTEMS, 1999, : 439 - 442
  • [44] Yield-limiting NMOSFET gate depletion in a deep sub-micron CMOS process
    Karnett, M
    Qian, S
    Mitchell, T
    Subramaniam, V
    Sur, H
    Haby, B
    Brugge, H
    CHALLENGES IN PROCESS INTEGRATION AND DEVICE TECHNOLOGY, 2000, 4181 : 191 - 199
  • [45] Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices
    Semenov, O
    Sarbishaei, H
    Axelrad, V
    Sachdev, M
    MICROELECTRONICS JOURNAL, 2006, 37 (06) : 526 - 533
  • [46] SUB-MICRON TUNGSTEN GATE PROCESS COMPATIBLE WITH SILICON GATE PROCESS
    YAMAMOTO, N
    IWATA, S
    KOBAYASHI, N
    YAGI, K
    WADA, Y
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1984, 131 (03) : C85 - C85
  • [47] Test challenges for deep sub-micron technologies
    Cheng, KT
    Dey, S
    Rodgers, M
    Roy, K
    37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000, 2000, : 142 - 149
  • [48] Deep sub-micron signal integrity challenge
    Kirkpatrick, Desmond A.
    Proceedings of the International Symposium on Physical Design, 1999, : 4 - 7
  • [49] SUB-MICRON RESOLUTION DEEP UV PHOTOLITHOGRAPHY
    VOSHCHENKOV, AM
    HERRMANN, H
    ELECTRONICS LETTERS, 1981, 17 (02) : 61 - 62
  • [50] Deep sub-micron bus invert coding
    Lindkvist, T
    Löfvenberg, J
    Gustafsson, O
    NORSIG 2004: PROCEEDINGS OF THE 6TH NORDIC SIGNAL PROCESSING SYMPOSIUM, 2004, 46 : 133 - 136