Source/drain engineering for parasitic resistance reduction for germanium p-MOSFETs

被引:17
|
作者
Chao, Yu-Lin [1 ]
Woo, Jason C. S. [1 ]
机构
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
关键词
copper germanide; germanium; MOSFET; parasitic resistance; preamorphization implantation (PAI);
D O I
10.1109/TED.2007.904576
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A reduction of parasitic resistance is presented with incorporation of preamorphization implantation (PAI) and self-aligned CU3Ge in the source/drain region for germanium p-MOSFETs. Full activation of boron in the amorphous layer can be obtained during solid-phase epitaxial growth, and a concentration as high as 4 x 10(20)/cm(3), is achieved. This non-thermal equilibrium concentration is maintained during the subsequent CU3Ge formation. Cu3Ge is adopted as a contact metal in germanium p-MOSFETs for the first time, due to its superior electrical properties (6.8 mu ohm center dot ern for resistivity and similar to 1 x 10(-7) ohm center dot cm(2) on p-type germanium for specific contact resistance). The fabricated p(+)/n diode yields a five order of magnitude between forward and reverse currents, which can be attributed to the reduction in parasitic resistance. The low reverse current mitigates concerns of possible deep-level traps introduced by copper. It also confirms the nonexistence of extended defects created by PAI as a result of the unique role of vacancies in germanium. With high dopant concentrations achieved by PAI and low resistance Of Cu3Ge, excellent MOSFET characteristics are demonstrated in self-aligned CU3Ge p-MOSFETs. A 15% mobility enhancement over Si universal mobility and a 60% parasitic resistance reduction are achieved.
引用
收藏
页码:2750 / 2755
页数:6
相关论文
共 50 条
  • [21] Optimization of p-MOSFETs featuring uniaxial stress induced by Si1-xGex source/drain and SDE
    Yuan, Jiahui
    Zhu, Guangping
    Wang, Jinpeng
    Zou, Jianping
    Tian, Lilin
    2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS, 2005, : 119 - 122
  • [22] High-Performance Germanium p- and n-MOSFETs With NiGe Source/Drain
    Chen, Che-Wei
    Tzeng, Ju-Yuan
    Chung, Cheng-Ting
    Chien, Hung-Pin
    Chien, Chao-Hsin
    Luo, Guang-Li
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (08) : 2656 - 2661
  • [23] New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs
    Wu, Shu-Hua
    Yu, Chang-Hung
    Su, Pin
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2015, 3 (06): : 441 - 446
  • [24] Asymmetric InGaAs/InP MOSFETs With Source/Drain Engineering
    Mo, Jiongjiong
    Lind, Erik
    Wernersson, Lars-Erik
    IEEE ELECTRON DEVICE LETTERS, 2014, 35 (05) : 515 - 517
  • [25] New Observations in LOD Effect of 45-nm P-MOSFETs With Strained SiGe Source/Drain and Dummy Gate
    Cheng, Chung-Yun
    Fang, Yean-Kuen
    Hsieh, Jang-Cheng
    Yang, Sheng-Jier
    Sheu, Yi-Ming
    Hsia, Harry
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (08) : 1618 - 1623
  • [26] Computational Study of Geometrical Designs for Source/Drain Contacts to Reduce Parasitic Resistance in Extremely Scaled MOSFETs
    Kim, Raseong
    Avci, Uygar E.
    Young, Ian A.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (03) : 1189 - 1196
  • [27] Electrical characteristics of n- and p-MOSFETs with gates crossing source/drain regions at 90 degrees and 45 degrees
    Ohzone, T
    Matsuyama, N
    IEICE TRANSACTIONS ON ELECTRONICS, 1996, E79C (02) : 172 - 178
  • [28] SOURCE-AND-DRAIN SERIES RESISTANCE OF LDD MOSFETS
    SHEU, BJ
    HU, C
    KO, PK
    HSU, FC
    IEEE ELECTRON DEVICE LETTERS, 1984, 5 (09) : 365 - 367
  • [29] NEW OBSERVATION AND THE MODELING OF GATE AND DRAIN CURRENTS IN OFF-STATE P-MOSFETS
    CHEN, MJ
    CHAO, KC
    CHEN, CH
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (05) : 734 - 739
  • [30] Extraction of source and drain resistances in MOSFETs using parasitic bipolar junction transistor
    Kim, HT
    Nam, IC
    Kim, KS
    Kim, KH
    Choi, JB
    Lee, JU
    Kim, SW
    Kang, GC
    Kim, DJ
    Min, KS
    Kang, DW
    Kim, DM
    ELECTRONICS LETTERS, 2005, 41 (13) : 772 - 774