Noise Optimization of CMOS Front-End Amplifier for Embedded Biomedical Recording

This paper deals with the noise optimization of a low-power front-end amplifier (FEA) integrating a band-pass filter for EEG signal recording. The AC-coupled and capacitive feedback structures have been adopted in order to reject the large DC offset generated at the electrode-skin interface. A high open-loop gain with acceptable phase margin was obtained with the proposed operational transconductance amplifier architecture. The methodology to reach a low noise-to-power trade-off is based on selecting the suitable operation region of each transistor, especially the input differential pair by considering the g(m)/I-D parameter. The proposed amplifier was implemented in both 0.13 mu m and 0.18 mu m CMOS processes with a supply voltage set to +/- 1 V. For both technologies, the obtained gain and bandwidth are practically similar, while the phase margin obtained in the first process (0.13 mu m) is higher than the one obtained in the second process (0.18 mu m); however, both values insure system stability. A lower total input-referred noise of 1.7 mu V-rms with a noise efficiency factor of 3.4 was obtained in 0.18 mu m CMOS process. The designed FEA has been found suitable for ECG biopotential recording.