Process Control for 45 nm CMOS logic gate patterning

被引：0

作者：

Le Gratiet, Bertrand ^{[1
]}

Gouraud, Pascal ^{[1
]}

Aparicio, Enrique ^{[1
]}

Babaud, Laurene ^{[1
]}

Dabertrand, Karen ^{[1
]}

Touchet, Mathieu ^{[1
]}

Kremer, Stephanie ^{[3
]}

Chaton, Catherine ^{[2
]}

Foussadier, Franck ^{[1
]}

Sundermann, Frank ^{[1
]}

Massin, Jean ^{[1
]}

Chapon, Jean-Damien ^{[1
]}

Gatefait, Maxime ^{[1
]}

Minghetti, Blandine ^{[1
]}

de-Caunes, Jean ^{[1
]}

Boutin, Daniel ^{[1
]}

机构：

[1] STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles, France

[2] CEA Leti, F-38054 Grenoble 9, France

[3] KLA Tencor, F-38920 Meylan, France

来源：

METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXII, PTS 1 AND 2 | 2008年 / 6922卷 / 1-2期

关键词：

45nm logic gate; immersion lithography; scatterometry; CD uniformity;

D O I：

10.1117/12.776889

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

引用

页数：11

共 50 条

[41] Advanced process control for 40nm Gate fabrication
Tajima, M
Arimoto, H
Goto, TK
Harada, F
2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS, 2003, : 115 - 118
[42] 45nm High-k + Metal Gate Strain-Enhanced CMOS Transistors
Auth, Chris
PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2008, : 379 - 386
[43] Design and Analysis of Leakage Current and Delay for Double Gate MOSFET at 45nm in CMOS Technology
Manorama
Shrivastava, Pavan
Akashe, Shyam
7TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO 2013), 2013, : 301 - 306
[44] Dielectric breakdown in a 45 nm high-k/metal gate process technology
Prasad, C.
Agostinelli, M.
Auth, C.
Brazier, M.
Chau, R.
Dewey, G.
Ghani, T.
Hattendorf, M.
Hicks, J.
Jopling, J.
Kavalieros, J.
Kotlyar, R.
Kuhn, M.
Kuhn, K.
Maiz, J.
McIntyre, B.
Metz, M.
Mistry, K.
Pae, S.
Rachmady, W.
Ramey, S.
Roskowski, A.
Sandford, J.
Thomas, C.
Wiegand, C.
Wiedemer, J.
2008 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 46TH ANNUAL, 2008, : 667 - +
[45] 75% Efficient Wide Bandwidth Grating Couplers in a 45 nm Microelectronics CMOS Process
Wade, Mark T.
Pavanello, Fabio
Kumar, Rajesh
Gentry, Cale M.
Atabaki, Amir
Ram, Rajeev
Stojanovic, Vladimir
Popovic, Milos A.
2015 IEEE OPTICAL INTERCONNECTS CONFERENCE, 2015, : 46 - 47
[46] CMOS scaling to 25 nm gate lengths
Kubicek, S
De Meyer, K
ASDAM '02, CONFERENCE PROCEEDINGS, 2002, : 259 - 270
[47] Impact of Gate Oxide Breakdown in Logic Gates from 28nm FDSOI CMOS technology
Saliva, M.
Cacho, F.
Ndiaye, C.
Huard, V.
Angot, D.
Bravaix, A.
Anghel, L.
2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2015,
[48] Design and fabrication of a CMOS MEMS logic gate
Tsai, Chun-Yin
Chen, Tsung-Lin
Liao, Hsin-Hao
Lin, Chen-Fu
Juang, Ying-Zong
MICROMACHINING AND MICROFABRICATION PROCESS TECHNOLOGY XVI, 2011, 7926
[49] Patterning Performance of Hyper NA Immersion Lithography for 32nm Node Logic Process
Takahata, Kazuhiro
Kajiwara, Masanari
Kitamura, Yosuke
Ojima, Tomoko
Satake, Masaki
Fujise, Hiroharu
Seino, Yuriko
Ema, Tatsuhiko
Takakuwa, Manabu
Nakagawa, Shinichiro
Kono, Takuya
Asano, Masafumi
Kyo, Suigen
Nomachi, Akiko
Harakawa, Hideaki
Ishida, Tatsuya
Hasegawa, Shunsuke
Miyashita, Katsura
Murakami, Takashi
Nagahara, Seiji
Takeda, Kazuhiro
Mimotogi, Shoji
Inoue, Soichi
LITHOGRAPHY ASIA 2008, 2008, 7140
[50] Conformal Metal Gate Process Technology for 14nm Logic Node and Below
Noori, A. M.
Brand, A.
Lei, Y.
Chen, M.
Tang, W.
Lu, X.
Fu, X.
Ganguli, S.
Anthis, J.
Thompson, D.
Yoshida, N.
Xu, M.
Allen, M.
Yang, H.
Gelatos, J.
Yu, S. -H.
Chang, M.
Gandikota, S.
DIELECTRIC MATERIALS AND METALS FOR NANOELECTRONICS AND PHOTONICS 10, 2012, 50 (04): : 171 - 176

← 1 2 3 4 5 →