Process Control for 45 nm CMOS logic gate patterning

被引：0

作者：

Le Gratiet, Bertrand ^{[1
]}

Gouraud, Pascal ^{[1
]}

Aparicio, Enrique ^{[1
]}

Babaud, Laurene ^{[1
]}

Dabertrand, Karen ^{[1
]}

Touchet, Mathieu ^{[1
]}

Kremer, Stephanie ^{[3
]}

Chaton, Catherine ^{[2
]}

Foussadier, Franck ^{[1
]}

Sundermann, Frank ^{[1
]}

Massin, Jean ^{[1
]}

Chapon, Jean-Damien ^{[1
]}

Gatefait, Maxime ^{[1
]}

Minghetti, Blandine ^{[1
]}

de-Caunes, Jean ^{[1
]}

Boutin, Daniel ^{[1
]}

机构：

[1] STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles, France

[2] CEA Leti, F-38054 Grenoble 9, France

[3] KLA Tencor, F-38920 Meylan, France

来源：

METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXII, PTS 1 AND 2 | 2008年 / 6922卷 / 1-2期

关键词：

45nm logic gate; immersion lithography; scatterometry; CD uniformity;

D O I：

10.1117/12.776889

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

引用

页数：11

共 50 条

[11] Double-Gate CMOS evaluation for 45nm technology node
Chiang, MH
An, JX
Krivokapic, Z
Yu, B
NANOTECH 2003, VOL 2, 2003, : 326 - 329
[12] Analyzing the Impact of Double Patterning Lithography on SRAM Variability in 45nm CMOS
Joshi, Vivek
Wieckowski, Michael
Chen, Gregory K.
Blaauw, David
Sylvester, Dennis
IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, 2010,
[13] Implementation of high-k and metal gate materials for the 45 nm node and beyond:: gate patterning development
Beckx, S
Demand, M
Locorotondo, S
Henson, K
Claes, M
Paraschiv, V
Shamiryan, D
Jaenen, P
Boullart, W
Degendt, S
Biesemans, S
Vanhaelemeersch, S
Vertommen, J
Coenegrachts, B
MICROELECTRONICS RELIABILITY, 2005, 45 (5-6) : 1007 - 1011
[14] High-K Metal Gate Contact RRAM (CRRAM) in Pure 28nm CMOS Logic Process
Shen, Wen Chao
Mei, Chin Yu
Chih, Y. -D.
Sheu, Shyh-Shyuan
Tsai, Ming-Jinn
King, Ya-Chin
Lin, Chrong Jung
2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2012,
[15] OVERVIEW OF GATE LINEWIDTH CONTROL IN THE MANUFACTURE OF CMOS LOGIC CHIPS
CHESEBRO, DG
ADKISSON, JW
CLARK, LR
ESLINGER, SN
FAUCHER, MA
HOLMES, SJ
MALLETTE, RP
NOWAK, EJ
SENGLE, EW
VOLDMAN, SH
WEEKS, TW
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1995, 39 (1-2) : 189 - 200
[16] Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology
Yuan, Xiaobin
Park, Jae-Eun
Wang, Jing
Zhao, Enhai
Ahlgren, David C.
Hook, Terence
Yuan, Jun
Chan, Victor W. C.
Shang, Hulling
Liang, Chu-Hsin
Lindsay, Richard
Park, Sungjoon
Choo, Hyotae
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2008, 8 (03) : 501 - 508
[17] 45-nm gate length CMOS technology and beyond using steep halo
Wakabayashi, H
Ueki, M
Narihiro, M
Fukai, T
Ikezawa, N
Matsuda, T
Yoshida, K
Takeuchi, K
Ochiai, Y
Mogami, T
Kunio, T
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 49 - 52
[18] Technology innovations and process integrations for sub-100nm gate patterning
Wilfred Pau
Nicolas Gani
Shashank Deshmukh
Thorsten Lill
Theodoros Panagopoulos
John Holland
半导体技术, 2004, (08) : 74 - 79
[19] Single metal gate on high-k gate stacks for 45nm low power CMOS
Taylor, W. J., Jr.
Capasso, C.
Min, B.
Winstead, B.
Verret, E.
Loiko, K.
Gilmer, D.
Hegde, R. I.
Schaeffer, J.
Luckowski, E.
Martinez, A.
Raymond, M.
Happ, C.
Triyoso, D. H.
Kalpat, S.
Haggag, A.
Roan, D.
Nguyen, J. -Y.
La, L. B.
Hebert, L.
Smith, J.
Jovanovic, D.
Burnett, D.
Foisy, M.
Cave, N.
Tobin, P. J.
Samavedam, S. B.
White, B. E., Jr.
Venkatesan, S.
2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 366 - +
[20] A 45 nm gate length high performance SOI transistor for 100nm CMOS technology applications
Celik, M
Krishnan, S
Fuselier, M
Wei, A
Wu, D
En, B
Cave, N
Abramowitz, P
Min, B
Pelella, M
Yeh, P
Burbach, G
Taylor, B
Jeon, Y
Qi, WJ
Li, RG
Conner, J
Yeap, G
Woo, M
Mendicino, M
Karlsson, O
Wristers, D
2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, : 166 - 167

← 1 2 3 4 5 →