Process Control for 45 nm CMOS logic gate patterning

被引：0

作者：

Le Gratiet, Bertrand ^{[1
]}

Gouraud, Pascal ^{[1
]}

Aparicio, Enrique ^{[1
]}

Babaud, Laurene ^{[1
]}

Dabertrand, Karen ^{[1
]}

Touchet, Mathieu ^{[1
]}

Kremer, Stephanie ^{[3
]}

Chaton, Catherine ^{[2
]}

Foussadier, Franck ^{[1
]}

Sundermann, Frank ^{[1
]}

Massin, Jean ^{[1
]}

Chapon, Jean-Damien ^{[1
]}

Gatefait, Maxime ^{[1
]}

Minghetti, Blandine ^{[1
]}

de-Caunes, Jean ^{[1
]}

Boutin, Daniel ^{[1
]}

机构：

[1] STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles, France

[2] CEA Leti, F-38054 Grenoble 9, France

[3] KLA Tencor, F-38920 Meylan, France

来源：

METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXII, PTS 1 AND 2 | 2008年 / 6922卷 / 1-2期

关键词：

45nm logic gate; immersion lithography; scatterometry; CD uniformity;

D O I：

10.1117/12.776889

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

引用

页数：11

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