A Characterized Redistribution Layer Architecture for Advanced Packaging Technologies

被引：6

作者：

Kudo, Hiroshi ^{[1
]}

Takano, Takamasa ^{[1
]}

Tanaka, Masaya ^{[1
]}

Kasai, Ryohhei ^{[1
]}

Suyama, Jyunichi ^{[1
]}

Akazawa, Miyuki ^{[2
]}

Takeda, Mitsuhiro ^{[1
]}

Mawatari, Hiroshi ^{[2
]}

Sasao, Toshio ^{[2
]}

Okazaki, Yumi ^{[1
]}

Oota, Naoki ^{[3
]}

Tashiro, Susumu ^{[4
]}

Iida, Haruo ^{[1
]}

Sakamoto, Kouji ^{[1
]}

Sato, Hiroyuki ^{[1
]}

Kitayama, Daisuke ^{[1
]}

Yamada, Shouhei ^{[1
]}

Kuramochi, Satoru ^{[1
]}

机构：

[1] DNP Co Ltd, Microelect Technol Dept, 250-1 Wakashiba, Kashiwa, Chiba 2770871, Japan

[2] DNP Co Ltd, Fine Optron Operat, 250-1 Wakashiba, Kashiwa, Chiba 2770871, Japan

[3] DNP Co Ltd, Mobil Technol Dept, 250-1 Wakashiba, Kashiwa, Chiba 2770871, Japan

[4] DNP Co Ltd, MEMS Ctr, 250-1 Wakashiba, Kashiwa, Chiba 2770871, Japan

来源：

2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2016年

关键词：

component; redistribution layer; 2.5D interposer; wafer level packaging; semi-additive process; Cu damascene; Transmission loss; Reliability; ELECTROMIGRATION;

D O I：

10.1109/ECTC.2016.69

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An enhanced redistribution layer architecture has been developed in which the Cu wires are directly covered with a double layer consisting of two types of dielectrics by using a semi-additive process. The double layer enhanced the thermal and electrical reliabilities of the Cu wires. Moreover, it enabled fabrication of a single-sided nine-level redistribution layer embedded with a fully stacked via. This greatly increased wiring layout flexibility and enhanced the transmission rate. Characterization of this architecture revealed that it has several advantages for advanced packaging technologies including a 2.5D interposer.

引用

页码：2063 / 2067

页数：5

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