Monolithic time-to-digital converter with 20ps resolution

被引：26

作者：

Tisa, S ^{[1
]}

Lotito, A ^{[1
]}

Giudice, A ^{[1
]}

Zappa, F ^{[1
]}

机构：

[1] Politecn Milan, Dipartimento Elettron & Informat, I-20133 Milan, Italy

来源：

ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSCIRC.2003.1257173

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a fully-integrated Time-to-Digital Converter, in a standard 0.8mum-CMOS technology, based on a cyclic pulse-shrinking design, that provides the lowest channel width of 20ps ever reported in literature for single-shot measurements performed by monolithic circuits, with differential linearity errors lower than 10ps (less than 0.5 LSB), conversion time shorter than 20mus, and 18ns Full-Scale-Range.

引用

页码：465 / 468

页数：4

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