Dependable design technique for system-on-chip

被引：11

作者：

Kubalik, Pavel ^{[1
]}

Kubatova, Hana ^{[1
]}

机构：

[1] Czech Tech Univ, Dept Comp Sci & Engn, Fac Elect Engn, Prague 12135 2, Czech Republic

来源：

JOURNAL OF SYSTEMS ARCHITECTURE | 2008年 / 54卷 / 3-4期

关键词：

reliable digital design; FPGA; dependability model; dependability calculations; on-line testing; fault security; self-testing; totally self-checking; single even upset; reconfiguration;

D O I：

10.1016/j.sysarc.2007.09.003

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based oil a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters. (C) 2007 Elsevier B.V. All rights reserved.

引用

页码：452 / 464

页数：13

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