Design Space Exploration for Three-dimensional Network-on-chip

被引：0

作者：

Wu, Ji ^{[1
]}

Xie, Dong-qing ^{[1
]}

机构：

[1] Guangzhou Univ, Sch Comp Sci & Educ Software, Guangzhou 510006, Guangdong, Peoples R China

来源：

2015 INTERNATIONAL CONFERENCE ON SOFTWARE, MULTIMEDIA AND COMMUNICATION ENGINEERING (SMCE 2015) | 2015年

关键词：

3D IC design; 3D partition; Cost analysis; PERFORMANCE;

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Cost is crucial to volume production of a new technology. Fabrication cost model of 3D IC is studied in this paper, and we find that 3D partition plays an important role in fabrication costs of 3D ICs. The main contribution of this paper is the conclusion of a cost-driven partition method which comes from a lot of experiments. The best way to achieve the least fabrication cost is to divide the circuit into several dies whose areas are optimal. The optimal area is affected by many factors, and can be calculated under a certain circumstance. Using this conclusion, fabrication costs of 2D and 3D ICs are evaluated and the latter show economic superiority when the gate number of IC is large.

引用

页码：129 / 134

页数：6

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