Sensing design issues in deep submicron CMOS SRAMs

被引：4
|
作者：
Natarajan, A [1 ]
Shankar, V [1 ]
Maheshwari, A [1 ]
Burleson, W [1 ]
机构：
[1] Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA
来源：
IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW FRONTIERS IN VLSI DESIGN | 2005年
关键词：
D O I：
10.1109/ISVLSI.2005.67
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, solutions to memory design issues in nanometer CMOS are presented. First a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved Bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of upto 68% can be obtained using this technique.
引用
收藏
页码：42 / 45
页数：4
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