Sensing design issues in deep submicron CMOS SRAMs

被引：4

作者：

Natarajan, A ^{[1
]}

Shankar, V ^{[1
]}

Maheshwari, A ^{[1
]}

Burleson, W ^{[1
]}

机构：

[1] Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA

来源：

IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW FRONTIERS IN VLSI DESIGN | 2005年

关键词：

D O I：

10.1109/ISVLSI.2005.67

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, solutions to memory design issues in nanometer CMOS are presented. First a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved Bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of upto 68% can be obtained using this technique.

引用

页码：42 / 45

页数：4

共 50 条

[21] Design methodology of deep submicron CMOS devices for 1V operation
Oyamatsu, H
Kinugawa, M
Kakumu, M
IEICE TRANSACTIONS ON ELECTRONICS, 1996, E79C (12) : 1720 - 1725
[22] Issues for Fabless Design Companies moving towards deep submicron system on a chip design
Coston, WT
IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS, 1998, : 581 - 587
[23] Tradeoffs in submicron CMOS process design
Cochran, Bill, 1600, (14):
[24] Multiple Bit Upsets and Error Mitigation in Ultra-Deep Submicron SRAMS
Mavis, D. G.
Eaton, P. H.
Sibley, M. D.
Lacoe, R. C.
Smith, E. J.
Avery, K. A.
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008, 55 (06) : 3288 - 3294
[25] Amplifier Design Approximations in Submicron CMOS
Mal, Ashis Kumar
Mal, Agnish
2016 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, COMPUTING AND COMMUNICATIONS (MICROCOM), 2016,
[26] Experimental studies on deep submicron CMOS scaling
IBM Corp, Fishkill, United States
Semicond Sci Technol, 7 (816-820):
[27] Experimental studies on deep submicron CMOS scaling
Chen, K
Hu, C
Fang, P
Gupta, A
Lin, MR
Wollesen, DL
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 1998, 13 (07) : 816 - 820
[28] An Evaluation of CMOS Adders in Deep Submicron Processes
Gera, Rahul J.
Hoe, David H. K.
2012 44TH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY (SSST), 2012, : 126 - 129
[29] Analysis of harmonic distortion in deep submicron CMOS
Bucher, M
Bazigos, A
Nastos, N
Papananos, Y
Krummenacher, F
Yoshitomi, S
ICECS 2004: 11TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, 2004, : 395 - 398
[30] Leakage scaling in deep submicron CMOS for SoC
Lin, YS
Wu, CC
Chang, CS
Yang, RP
Chen, WM
Liaw, JJ
Diaz, CH
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (06) : 1034 - 1041

← 1 2 3 4 5 →