Evaluating BIST architectures for low power

The "system-on-chip" revolution has posed a number of new challenges to the test engineers. We address the issue of high power dissipation during testing, which can reach levels that are beyond the safe upper Limit associated with the chosen packaging technology. A study undertaken by Zorian reveals that test power can be as large as 200% or more in comparison to the normal power. In the test mode, input vectors are normally applied in an uncorrelated manner, leading to an increase in the average Hamming distance between two successive vectors. This implies a larger switching activity, and, for CMOS circuits, implies a larger power dissipation. In this paper, our attempt is to look at Built-in Self-Test architectures from the view point of power dissipation, fault-coverage, area, and test length. We report experimental results for a CORDIC chip. Our results indicate that BIST architectures differ significantly from one another in terms of power dissipation, giving the test designer an opportunity to address the problem of excessive heating during testing.