High-Speed VLSI Implementation of an Improved Parallel Delayed LMS Algorithm

Motivated by improvement of convergence rate and throughput performance, this work develops a systematic high-speed VLSI implementation of the adaptive filter based on the improved 2-parallel delayed LMS (PDLMS) algorithm. The proposed design uses a novel hardware-efficient architecture for weight updating based on parallel adaptive 2-by-2 algorithm. Compared with the conventional filter structure, the parallel filter has higher throughput rate and lower power dissipation. To improve the convergent characteristic of the adaptive digital filter, we have selected one branch from two weight update branches which has better system performance. The fine-grained arithmetic operation unit and the retiming technology are employed to reduce the delay of critical path effectively. From the ASIC synthesis results we find that the proposed architecture of an 8-tap filter has nearly 24% less power and nearly 18% less area-delay-product (ADP) than the best existing structure. Thus it can be seen that the proposed design has the important practice instruction significance.