VLSI design and implementation of a high-speed multicast switch fabric

被引：0

作者：

Li, C. ^{[1
]}

Venkatesan, R. ^{[1
]}

Heys, H. M. ^{[1
]}

机构：

[1] Mem Univ Newfoundland, Fac Engn & Appl Sci, St John, NF A1B 3X5, Canada

来源：

2006 23RD BIENNIAL SYMPOSIUM ON COMMUNICATIONS | 2006年

基金：

加拿大自然科学与工程研究理事会;

关键词：

multicast; Balanced Gamma (BG) switch; VLSI design; CMOS technology; multistage interconnection network (MIN); scalability;

D O I：

暂无

中图分类号：

TN [电子技术、通信技术];

学科分类号：

0809 ;

摘要：

This paper presents the VLSI design and implementation of a new cell-based high-speed multicast switch fabric using the 0.18 mu m CMOS technology. Using distributed control, multistage interconnection network structure, and modular design, the multicast Balanced Gamma (BG) switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non-uniform traffic conditions. The BG switch follows predominantly an output-buffered architecture and utilizes a self-replication mechanism for multicast traffic switching. In the paper, we discuss in detail the front-end design issues of the switch using the ASIC design flow recommended by the Canadian Microelectronics Corporation (CMC) [1]. Synthesized results are provided for measures of circuit complexity and timing.

引用

页码：356 / +

页数：2

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