Design and verification of high-speed VLSI physical design

被引：0

作者：

Zhou, D ^{[1
]}

Li, RM

机构：

[1] Univ Texas, Dept Elect Engn, Richardson, TX 75083 USA

[2] Fudan Univ, Sch Microelect, Shanghai 200433, Peoples R China

来源：

JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY | 2005年 / 20卷 / 02期

关键词：

VLSI; physical design; floorplanning and placement; interconnect; delay; wire sizing; buffer insertion; power; order reduction; power grid; parameter extraction; clock distribution;

D O I：

10.1007/s11390-005-0147-5

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.

引用

页码：147 / 165

页数：19

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