Design of 65 nm CMOS SRAM for Space Applications: a Comparative Study

被引：0

作者：

Gorbunov, Maxim S. ^{[1
,2
]}

Dolotov, Pavel S. ^{[1
]}

Antonov, Andrey A. ^{[1
]}

Zebrev, Gennady I. ^{[2
]}

Emeliyanov, Vladimir V. ^{[3
]}

Boruzdina, Anna B.

Petrov, Andrey G.

Ulanova, Anastasia V.

机构：

[1] Russian Acad Sci, Sci Res Inst Syst Anal, Nakhimovsky Prosp 36-1, Moscow 117218, Russia

[2] Natl Res Nucl Univ, Moscow Engn Phys Inst, Dept Micro & Nanoelect, Moscow, Russia

[3] Res Inst Scientif Instruments, Moscow, Russia

来源：

2013 14TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS (RADECS) | 2013年

关键词：

SEU; SBU; MCU; DICE; critical charge; SRAM; RHBD; heavy ions; protons; TID; CMOS; guard rings; HEAVY-ION; MITIGATION; CHARGE; UPSETS; BULK;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We study the design of different SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the localization of a strike. DICE cells demonstrate about 2-3 orders of magnitude lower than cross-sections for 6T-cells due to the 2 mu m nodal spacing of sensitive pairs. Solid and intermittent guard rings has high effectiveness in SEL elimination.

引用

页数：7

共 50 条

[1] Design of 65 nm CMOS SRAM for Space Applications: A Comparative Study
Gorbunov, Maxim S.
Dolotov, Pavel S.
Antonov, Andrey A.
Zebrev, Gennady I.
Emeliyanov, Vladimir V.
Boruzdina, Anna B.
Petrov, Andrey G.
Ulanova, Anastasia V.
[J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2014, 61 (04) : 1575 - 1582
[2] Radiation-Induced Mismatch Enhancement in 65 nm CMOS SRAM for Space Applications
Gorbunov, Maxim S.
Dolotov, Pavel S.
Shnaider, Alexandra I.
Zebrev, Gennady I.
Antonov, Andrey A.
Lebedev, Anatoly A.
[J]. INTERNATIONAL CONFERENCE ON MICRO- AND NANO-ELECTRONICS 2014, 2014, 9440
[3] COMPARATIVE ANALYSIS OF SENSE AMPLIFIERS FOR SRAM IN 65nm CMOS TECHNOLOGY
Chandoke, Nidhi
Chitkara, Neha
Grover, Anuj
[J]. 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND COMMUNICATION TECHNOLOGIES, 2015,
[4] A new write assist technique for SRAM design in 65 nm CMOS technology
Farkhani, Hooman
Peiravi, Ali
Moradi, Farshad
[J]. INTEGRATION-THE VLSI JOURNAL, 2015, 50 : 16 - 27
[5] A SRAM design on 65nm CMOS technology with integrated leakage reduction scheme
Zhang, K
Bhattacharya, U
Chen, Z
Hamzaoglu, F
Murray, D
Vallepalli, N
Wang, Y
Zheng, B
Bohr, M
[J]. 2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, : 294 - 295
[6] A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation
Ho, Weng-Geng
Zheng, Zixian
Chong, Kwen-Siong
Gwee, Bah-Hwee
[J]. 2018 IEEE 23RD INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP), 2018,
[7] Temperature Dependence of MCU Sensitivity in 65 nm CMOS SRAM
Boruzdina, Anna B.
Sogoyan, Armen V.
Smolin, Anatoly A.
Ulanova, Anastasia V.
Gorbunov, Maxim S.
Chumakov, Alexander I.
Boychenko, Dmitry V.
[J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2015, 62 (06) : 2860 - 2866
[8] Comparative Study of FinFETs versus 22nm Bulk CMOS technologies: SRAM Design Perspective
Farkhani, Hooman
Peiravi, Ali
Kargaard, Jens Madsen
Moradi, Farshad
[J]. 2014 27TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2014, : 449 - 454
[9] SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
Zhang, K
Bhattacharya, U
Chen, ZP
Hamzaoglu, F
Murray, D
Vallepalli, N
Wang, Y
Zheng, B
Bohr, M
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (04) : 895 - 901
[10] NOVEL CMOS SRAM VOLTAGE LATCHED SENSE AMPLIFIERS DESIGN BASED ON 65 nm TECHNOLOGY
Wei, Zikui
Peng, Xiaohong
Wang, Jinhui
Yin, Haibin
Gong, Na
[J]. 2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,

← 1 2 3 4 5 →