NOVEL CMOS SRAM VOLTAGE LATCHED SENSE AMPLIFIERS DESIGN BASED ON 65 nm TECHNOLOGY

被引：0

作者：

Wei, Zikui ^{[1
]}

Peng, Xiaohong ^{[1
]}

Wang, Jinhui ^{[1
]}

Yin, Haibin ^{[1
]}

Gong, Na ^{[2
]}

机构：

[1] Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China

[2] North Dakota State Univ, Dept Elect & Comp Engn, Fargo, ND 58102 USA

来源：

2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2014年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel voltage latched sense amplifier is proposed in this paper. It applies a self-closing bit-line module technique, which makes the input and output nodes separated to optimize sensing delay and power consumption. Initially, the size of transistors in the circuits is adjusted to speed up the circuit and lower the power. The simulation results show that the proposed design improves sensing when smaller bit-lines difference requires for full-swing amplification as the conventional voltage latched sense amplifier. The proposed design also improves power efficiency at least 30% as compared to the conventional voltage latched sense amplifier.

引用

页数：3

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