Machine learning approach to gate-level evolvable hardware

被引:0
|
作者
Iba, H [1 ]
Iwata, M [1 ]
Higuchi, T [1 ]
机构
[1] Electrotech Lab, Ibaraki, Osaka 305, Japan
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Evolvable Hardware (EHW) is a hardware which modifies its own hardware structure according to the environmental changes. EHW is implemented on a programmable logic device (PLD), whose architecture can be altered by downloading a binary bit string, i.e. architecture bits. The architecture bits are adaptively acquired by genetic algorithms (GA). The target task of EHW is "Boolean concept formation", which has been intensively studied in machine learning literatures. Although many evolutionary or adaptive techniques were proposed to solve this class of problems, there have been very few comparative studies from the viewpoint of computational learning theory. This paper describes machine learning approach to the gate-level EHW, i.e. 1) MDL-based improvement of fitness evaluation, and 2) comparative studies of efficiency by PAC criterion. We also discuss the current extension of EHW and related works.
引用
收藏
页码:327 / 343
页数:17
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