Very high-speed Reed-Solomon decoders

被引：1

作者：

Sarwate, DV ^{[1
]}

Shanbhag, NR ^{[1
]}

机构：

[1] Univ Illinois, Coordinated Sci Lab, Urbana, IL 61801 USA

来源：

2000 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/ISIT.2000.866717

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A pipelined finite-field multiplier structure in conjunction with a single systolic array implementation of the Berlekamp-Massey algorithm leads to a highly parallel decoder architecture in which the critical path delay is an order of magnitude smaller than the path delays of conventional architectures.

引用

页码：419 / 419

页数：1

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