Challenges for low-power and high-performance chips -: A D&T roundtable

Microprocessor and other IC performance continues to improve at historic rates, with no visible end in sight for the next 10 years. However, we are starting to encounter a power wall. This is true for high-performance components as well as for low-power chips with a very limited energy budget offered by batteries. We need to find ways to manage power and energy consumption on all Fronts-technology, design, and architecture without compromising performance. Otherwise, we may Face discontinuation of Moore's law for the semiconductor industry in the near future. This would be triggered not by any difficulty in the scaling of process technology bur by formidable barriers posed by packaging and cooling, inefficacy of power delivery, and energy constraints dictated by battery technology, which is advancing at a very lukewarm pace. IEEE Design & Test thanks roundtable participants Ching-Te Chuang (IBM), Shih-Lien Lu (Oregon State Univ.), Krishnamurthy Soumyanath (Inf el), Hamid Partovi (AMD), and Takayasu Sakurai (Univ. of Tokyo). D&T gratefully acknowledges the help of Vivek De (Intel), our moderator; Kaushik Roy (Purdue Univ.), our Roundtable Editor who organized the event; and Yibin Ye (Intel), who acted as our photographer. Special thanks go to the IEEE Computer Society's Test Technology Technical Committee (TTTC) for sponsoring this event and the VLSI Circuits Symposium for hosting it.