Promising complex ASIC design verification methodology

This paper aims at developing a design verification environment for complex application-specific integrated circuits (ASICs), with particular emphasis on embedded systems incorporating intellectual property (IP) cores. There exist methods to ensure correct design for IP core-based systems, but a promising approach to realize this is through the use of coverage-driven functional verification (CDV) and reuse methodology (RM). The CDV approach is based on the ASIC functionalities, and the verification process is accomplished in the early stages of the design. The use of functional coverage minimizes the number of test cases and thus enhances the verification process. The deterministic testing together with CDV and RM is applied to verify designs in the paper. The Specman e-language is used as a verification tool in the process since it incorporates the capabilities of both CDV and RM.