Implementation of a H.264/AVC SVC Decoder with Multi-symbol Prediction CAVLC for Advanced T-DMB Receiver

被引:1
|
作者
Kim, Dong-Sun [1 ]
Lee, Seung-Yerl [1 ]
Lee, Sang-Seol [1 ]
Ahn, Jae-Hun [1 ]
Cho, Byeong-Ho [1 ]
机构
[1] Korea Elect Technol Inst, Multimedia IP Res Ctr, Gyeonggi Do, Seongnam Si, South Korea
关键词
Scalable video coding; CAVLC decoder; multi-symbol decoder; VLSI; H.264/AVC; VLSI ARCHITECTURE; DESIGN;
D O I
10.1109/TCE.2010.5681174
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a low-cost high-performance H.264/AVC SVC decoder with multi-symbol prediction context-based adaptive variable length coding (CAVLC) for advanced T-DMB receiver. Proposed multi-symbol prediction CAVLC mainly consists of a simple arithmetic operation unit with reduced look-up tables and a leading zero detector. We also propose a multi-symbol run_before decoder and it decodes more than 2.5 symbols in a cycle. Gate count of a H.264/AVC SVC decoder is about 1,300K gates when synthesized with 0.18um CMOS process and it can be operated at 120MHz clock frequency. For the verification of a H.264/AVC SVC decoder chip, prototype mobile movie player systems have been implemented using a 7 inch LCD and USB controller(1).
引用
收藏
页码:2819 / 2825
页数:7
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