1.2 nm HfSiON/SiON stacked gate insulators for 65-nm-node MISFETs

We have investigated a Hf-based CMOSFET fabrication method that would enable the high performance and low gate leakage current that are required for the 65-nm-node CMOS devices. To suppress the gate leakage in a gate stack with an equivalent oxide thickness (EOT) of 1.2 nm, the upper layer of HfSiO film was thickened and nitrided. The nitridation improves the dielectric constant, allowing the use of a thicker HfSiO layer. The mobility was improved by lightly nitriding the bottom SiO2 interface layer, which suppresses the interfacial trap generation. Such techniques enabled us to achieve a good EOT vs I-g relationships. The I-g at an EOT of 1.2 nm was reduced by three orders of magnitude as compared with that with a SiO2 gate insulator. High mobilities, 87% of that of a SiO2 MOSFET for an NFET and 96% for a PFET, were also obtained.